FUNCTIONAL DESCRIPTION controlled. Furthermore, the digital filters are synchronized to start the convolution phase at the The ADS1274/78 is a delta-sigma ADC consisting of same modulator clock cycle. This design results in four/eight independent converters that digitize excellent phase match among the ADS1274/78 four/eight input signals in parallel. channels. The converter is composed of two main functional Figure 35 shows the inter-device channel sample blocks to perform the ADC conversions: the matching for the ADS1274 and ADS1278. modulator and the digital filter. The modulator samples the input signal together with sampling the The phase match of one 4-channel ADS1274 to that reference voltage to produce a 1s density output of another ADS1274 (eight or more channels total) stream. The density of the output stream is may not have the same degree of sampling match. proportional to the analog input level relative to the As a result of manufacturing variations, differences in reference voltage. The pulse stream is filtered by the internal propagation delay of the internal CLK signal internal digital filter where the output conversion coupled with differences of the arrival of the external result is produced. CLK signal to each device may cause larger sampling match errors. Equal length CLK traces or external In operation, the input signal is sampled by the clock distribution devices can be used to reduce the modulator at a high rate (typically 64x higher than the sampling match error between devices. final output data rate). The quantization noise of the modulator is moved to a higher frequency range FREQUENCY RESPONSE where the internal digital filter removes it. Oversampling results in very low levels of noise The digital filter sets the overall frequency response. within the signal passband. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high Since the input signal is sampled at a very high rate, stop band attenuation. The filter coefficients are input signal aliasing does not occur until the input identical to the coefficients used in the ADS1271. The signal frequency is at the modulator sampling rate. oversampling ratio of the digital filter (that is, the ratio This architecture greatly relaxes the requirement of of the modulator sampling to the output data rate, or external antialiasing filters because of the high fMOD/fDATA) is a function of the selected mode, as modulator sampling rate. shown in Table 3. SAMPLING APERTURE MATCHING Table 3. Oversampling Ratio versus Mode The ADS1274/78 converters operate from the same MODE SELECTION OVERSAMPLING RATIO (fMOD/fDATA) CLK input. The CLK input controls the timing of the High-Speed 64 modulator sampling instant. The converter is High-Resolution 128 designed such that the sampling skew, or modulator sampling aperture match between channels, is